90 lines
3.2 KiB
Plaintext
90 lines
3.2 KiB
Plaintext
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@verbatim
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******************************************************************************
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* @file st_readme.txt
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* @author MCD Application Team
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* @brief This file lists the main modification done by STMicroelectronics on
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* CMSIS_5 for integration with STM32Cube solution.
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******************************************************************************
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* Copyright 2024-2025 STMicroelectronics
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* ******************************************************************************
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@endverbatim
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### 20-May-2025 ###
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=======================
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Tag: v5.9.0_fix_620_dsp_v1.10.0_nn_v3.1.0_no_doc
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Remove Documentation/ subfolders and update index.html to link to
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online documentation https://arm-software.github.io/CMSIS_5/latest/General/html/index.html
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### 14-January-2025 ###
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=======================
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Tag: v5.9.0_fix_620_dsp_v1.10.0_nn_v3.1.0
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Update Core/Include/cachel1_armv7.h
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fix(cmsis): Integrate SCB_DisableDCache() issue 620 fixes from CMSIS_5 github
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Merge two following commits from https://github.com/ARM-software/CMSIS_5
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SHA-1: 36bd54f7963825954b3dd37c036dbbcd1494988f
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* Fix the endless loop issue with GCC O0.
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More details, see https://github.com/ARM-software/CMSIS_5/issues/620
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The issue only happens when local variables are in stack (GCC O0). If local variables are saved
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in general purpose register, then the function is OK.
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When local variables are in stack, after disabling the cache, flush the local variables cache
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line for data consistency.
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SHA-1: ae2a29fc077f2d62ad9c6793e19eea604bf76843
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* Core(M): Fix endless loop issue with non-optimized IAR builds
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This is an IAR fix for the problem described in
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https://github.com/ARM-software/CMSIS_5/issues/620
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IAR builds can not align the stack to the cache line size and
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thus the invalidation is done in separate steps for the three
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variables.
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Fix validated on STM32H7 HW.
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### 14-October-2024 ###
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=======================
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Tag: v5.9.0_dsp_v1.10.0_nn_v3.1.0
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CMSIS v5.9.0, please refer to "index.html" available under \Documentation folder.
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CMSIS v5.9.0, CMSIS-DSP v1.1.0, CMSIS-NN v3.1.0
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Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
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used in existing projects, and thus avoid projects mass update
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Note: the following components has been removed from ARM original delivery (not used in ST packages)
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- .gitattributes
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- .gitignore
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- \Device
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- CMSIS\DAP
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- \Firmware\Examples
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- \Firmware\Template
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- \Firmware\Validation
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- CMSIS\Driver
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- CMSIS\NN\Tests
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- CMSIS\RTOS\RTX
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- CMSIS\RTOS\Template
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- CMSIS\RTOS2\RTX
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- CMSIS\Utilities
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